[1]
“Accelerated FIR Filter Design on FPGAs Leveraging Specialized Compressor Architectures and Optimized Approximate Adders”, ijec, vol. 5, no. 01, pp. 9–13, Aug. 2025, Accessed: Dec. 04, 2025. [Online]. Available: https://www.academicpublishers.org/journals/index.php/ijec/article/view/5974