The continuous evolution of wireless communication systems toward sixth-generation paradigms has intensified the exploration of new waveforms capable of supporting extreme data rates, ultra-reliable links, and high mobility in challenging propagation environments. Among the most critical operating regimes under consideration are millimeter-wave and sub-terahertz frequency bands, where hardware imperfections, propagation losses, and time-varying channels pose fundamental obstacles to reliable transmission. Orthogonal Time Frequency Space modulation has emerged as a promising alternative to conventional orthogonal frequency division multiplexing due to its inherent robustness in doubly dispersive channels and its ability to exploit the delay-Doppler domain representation of wireless channels. At the same time, phase noise originating from local oscillators becomes increasingly detrimental at high carrier frequencies, manifesting as inter-carrier interference, common phase error, and loss of orthogonality. This article presents an extensive theoretical investigation into phase noise effects on OTFS-based communication systems operating in sub-THz and high-mobility scenarios. Drawing strictly on established literature, the study synthesizes propagation modeling, waveform design, channel estimation, synchronization, and phase noise compensation strategies into a unified analytical narrative. Emphasis is placed on understanding how OTFS fundamentally reshapes the impact of phase noise compared to OFDM, particularly in sparse delay-Doppler channels and under fractional Doppler conditions. The methodology integrates descriptive modeling of oscillator impairments, pilot-aided synchronization techniques, coherence bandwidth exploitation, and non-iterative compensation approaches adapted from OFDM to OTFS frameworks. Results are discussed qualitatively in terms of robustness trends, interference mitigation capabilities, and system-level performance implications without reliance on mathematical formalism. The discussion further explores theoretical limitations, trade-offs between complexity and robustness, and the relevance of emerging machine learning-based transceiver designs. The article concludes by positioning phase noise aware OTFS as a foundational waveform concept for future sub-THz mobile systems while identifying open research challenges in practical implementation and standardization.

The continuous scaling of very-large-scale integration technologies and the exponential growth of portable and high-performance computing systems have intensified the demand for digital arithmetic circuits that simultaneously achieve high speed, low power consumption, and robust reliability. Among these circuits, compressors play a pivotal role in arithmetic units such as multipliers, accumulators, and digital signal processors, where they significantly influence overall system performance and energy efficiency. This research article presents an in-depth theoretical and analytical investigation into low-power compressor architectures, focusing on 3-2, 4-2, and higher-order compressors as reported in foundational and contemporary literature. Drawing strictly from established references, this work synthesizes design philosophies based on CMOS logic, pass-transistor logic, XOR–XNOR gate optimization, multithreshold voltage schemes, and reduced transistor-count full adder structures. Rather than summarizing existing designs, the article elaborates extensively on the underlying principles that govern power dissipation, propagation delay, signal integrity, and scalability in compressor circuits. Methodological aspects are discussed from a conceptual design-analysis perspective, emphasizing transistor-level trade-offs without relying on equations or visual representations. The results section interprets reported outcomes in a descriptive manner, highlighting consistent trends across technologies and logic styles. The discussion critically evaluates limitations in prior approaches, such as voltage swing degradation and process variability sensitivity, while also exploring future design directions aligned with deep submicron and nanoscale technologies. The study concludes that low-power compressor optimization is not a single-technique problem but rather a holistic integration of logic style selection, threshold voltage engineering, and gate-level innovation. This article contributes a unified theoretical framework that can guide future compressor design for energy-efficient high-speed arithmetic systems.