This article addresses the issue of parallelizing digital signal processing methods based on the Haar transform using Andrews' algorithm on dual-core specialized processors. The study develops mechanisms for parallel execution of the fast Haar transform algorithm by effectively utilizing the hierarchical memory model, DMA controller, and core architecture of the Blackfin ADSP-BF561 processor. Algorithmic experiments were conducted in C++ using the VisualDSP++ platform, based on block-polynomial basis functions (constant, linear, quadratic). Practical tests compared performance between the single-core ADSP-BF533 and dual-core ADSP-BF561 processors, achieving speed-up coefficients ranging from 1.14 to 1.80. The results demonstrate that multi-core computing significantly improves signal processing efficiency and reduces processing time.

Fast Haar Transform (FHT), Andrews Algorithm, Parallel Computation, Dual-Core Processor, Blackfin ADSP-BF561, Digital Signal Processing (DSP), Piecewise Polynomial Basis Functions, VisualDSP++ Development Environment, Acceleration Coefficient.

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